1. The Field of the Invention
The present invention relates generally to mechanisms for two or more components to communicate using a two-wire interface. More specifically, the present invention relates to a two-wire interface having embedded per-frame reliability information for reliable communication between the two components.
2. Background and Relevant Art
Electronic and computing technology has transformed the way that we work and play. Many electronic or computing systems rely on a variety of components that cooperatively interact to perform complex functions. Such cooperative interaction often relies on the ability of the various components to communicate effectively.
There are many ways that electronic components may communicate. However, oftentimes a two-wire interface is used to communicate between components. Although communication using a two-wire interface can be slower than communication over other interfaces, the use of two-wire interfaces is preferred in some implementations because such interfaces often require less chip or board space between components. In addition, two-wire interfaces often introduce less electromagnetic interference in the rest of the chip and/or board than many parallel interfaces.
In some conventional two-wire interfaces, one wire is used to carry a clock signal, and one wire is used to carry a data signal. The clock signal is generally generated by a master component and is used by the master component as well as by one or more slave components. Either the master component or a slave component may drive data onto the data wire following the timing of the shared clock signal. Each communicating component understands a common two-wire protocol used to communicate, and thus may each function appropriately given the data. The data line for two-wire interfaces typically includes not only data, but also a header field that identifies the operations to be performed (i.e., the operation code), the device identifier (in cases in which there may be multiple slave components to communicate with), and an address from which the data should be read or to which the data should be written.
One example of a prolific two-wire interface is the I2C interface. The I2C interface may be used to transfer large amounts (e.g., kilobytes or megabytes) of data using a single corresponding header field. In other words, the header field is provided once, and the corresponding operation is understood to correspond to all of the data to follow. Since the header field is provided only once for large amounts of data, the I2C interface is very efficient when communicating large amounts of data to and from memory.
Another kind of two-wire interface includes a header field for each byte or word of data being transferred. Such two-wire interface will be referred to as a “guaranteed header two-wire interface” since each byte or word or other small fixed amount of data is guaranteed to have its own header field identifying the operation to be performed. Since each byte or word of data has its own header field, there is significantly more bandwidth used per unit of data transferred. Most often, in fact, there are more bits transferred that represent header information than there are that represent actual data to be read or written when using such guaranteed header interfaces. Accordingly, guaranteed header two-wire interfaces are not typically used for reading or writing large amounts of contiguous data. Instead, guaranteed header two wire interfaces are most often used for intermittently transferring small amounts of data as when, for example, occasionally setting configuration register values.
A frame of one conventional guaranteed header two-wire interface is illustrated in FIG. 7 and is often referred to as the “MDIO” interface. In this description and in the claims, a “frame” of a guaranteed header two-wire interface is defined as that the structural information used to transfer the corresponding one byte or word of data.
The master component begins the frame by affirmatively asserting a preamble on the data wire. The preamble includes 32 bits, each having a logical one (corresponding to bits 64:33). This preamble gives an indication to each of the one or more slave components that the other header information and data is about to be transmitted.
The master component then transmits the next two bits (corresponding to bits 32:31) have a logical zero to represent the start of the frame. This conveys that the more meaningful data is about to be transmitted.
In particular, after the start of frame bits, the master component transmits the operation code (corresponding to bits 30:29). Under the MDIO standard, an address operation corresponds to operation bit values of 00, a write operation corresponds to operation bit values of 01, a read operation corresponds to operation bit values of 11, and a read increment operation corresponds to operation bit values of 10.
The master component then transmits the port address (corresponding to bits 28:24). This identifies the slave port that is to be communicated with. Under the MDIO standard, more than one slave component may correspond to a single port. Accordingly, to uniquely identify the slave component to be communicated with, the master component then transmits a device identifier (corresponding to bits 23:19), to thereby allow that slave component to get ready to receive further information in the frame. This also allows any other slave components that are not to be communicated with to ignore the rest of the frame.
The next two clock cycles (corresponding to bits 18:17) are used to switch which component is asserting bits on the data wire. If the operation is an address or a write operation, the master component first transmits a logical one followed by a logical zero. If the operation is a read of a read increment operation, on the other hand, the master component lets the data wire float with a high impedance. This provides a transition cycle for the master component to release control of the data wire, and allows the slave component to drive the data wire with a logical zero in the following cycle thereby allowing the slave component to acquire control of the data wire.
If the operation is an address operation, the master component then indicates the address (corresponding to bits 16:01) that is to be operated on in a subsequent operation. If the operation is a write operation, the master component then writes the data (corresponding to bits 16:01) to an address specified in a previous address operation. If the operation is a read operation, the slave component then places the read data (corresponding to bits 16:01) from the previously specified address on the data wire. If the operation is a read increment operation, the slave component places the read data (corresponding to bits 16:01) for the next contiguous address on the data wire.
Regardless of the component is in control of the data wire, the component then lets the data wire float (corresponding to bit 00). This completes the frame.
The MDIO interface is effective in transferring data for the most part. However, there is provided no space for reliability data to be included, other than in the data field itself. Furthermore, for an address operation, reliability information cannot be included even in the data field. For example, there is no cyclic redundancy checking information or acknowledgements of successful operation. Accordingly, if there is a deficiency in the communication, or implementation of the operation, the master component may never be informed of the same, and thus may continue operating on the mistaken assumption that the operation has completed. Alternatively, the reliability information may be included as part of the data. However, the use of that reliability information would require a layer of logic that recognized the data as reliability information. This would also reduce the space available for the core data of interest that is unrelated to reliability information.
What would be advantageous is a guaranteed header two-wire interface in which reliability information may be included in the header information to allow for more reliable communications between components.